SUMMARY: Principal Systems and Mixed Signal Design and Verification Engineer extensive experience in DSP, Circuit Design, MIPI, Camera and Display, Efuse, SerDes, Solar Photo Voltaic Design, Utility Load Distribution, Automotive, Pre-silicon verification and Post-Si bench validation. Low power modes. Experience with all aspects of architecture, design, verification and validation on IC and board levels. Experience with high-speed I/O and module circuitry. WLAN, FM. Contributed successfully in design, test and manufacturing products. Sensors, Accelerometer, Gyroscope Controls, EMI, EMC.
Proficiencies include:
• Strong signal processing and analytical solving skills
• Sensors and Systems Integration and Architecture
• Digital/Analog Circuit Design and Simulators
• Superior Mixed-Signal and Analog Verification, Validation, Characterization and Test
• Strong Chip Manufacturing Experience and RTL Design
• Excellent customer relationships, very good communication skills
• Leadership, Decision Making Skills, Project Ownership
Patents – US 7,680,231B2: Adaptive Variable Length Pulse Synchronizer
Two patents pending – MIPI Camera and Display TXRX - FSL Wireless Division
Master's Thesis - Accelerometer Analog Control Loop with DSP Digital Filters
Program Languages Comprehended – SystemVerilog, Verilog, Verilog-AMS, RTL Design, C, SPICE, Cadence Packages, UNIX, Windows, Motorola processors, TMS320 series, AWI and VVW Verilog. Familiar with Mathematica, Python and Perl
Systems –PV, Utility PowerDSP Control Systems, Cameras, Displays, ASIC design, Gyroscopes, UAV, Accelerometers, Automotive, Wireless Basebands, Radar, Solar, Motor Control, Microprocessors, Microwave, Radio Transceivers for 1 - 5GHz
Modules –Camera and Video Display, Open and Closed Control Systems, DSP Controls, EFUSE, Receivers, DDR/MIPI, High-Speed I/O, Memories, PWM, I/O Pads, Voltage and Band-gap References, PLL, DLL, Amplifiers, Video, Image Processing, Voltage References, Chip Layout, High Frequency Communication, Asynchronous Circuitry, D/A, A/D, CODEC, Speaker Modeling, Over-Current
Overall Technical Experience – Testbench, Analog, Digital and Mixed Signal Design, Verification Lead, Validation, GHz Circuit Board Design, Test Lead, Product Engineering, Characterization, Applications, Module Ownership, PCB Design
Manufacturing – Full manufacture and qualification of two IC products and PCBs.
PROFESSIONAL EXPERIENCE
Dialog Semiconductor, San Jose CA/Phoenix, AZ April 2015 - September 2015
Engineer IV Verification Architect Engineer - Contract
• Mixed Signal Modeling PMIC/BuckCharger Verification Engineer
• Cadence-AMS in-depth configuration
Qualcomm, San Jose/San Diego, CA September 2013 - January 2015
Engineer IV Verification Architect Engineer - Contract
• Mixed Signal Modeling RX/TX WLAN Verification Engineer
• Verification Engineer – Analog Mixed-Signal – Codec Chip
• Digital Filters, PWM, Over-Current Protection, AWI and VVW based Verilog
Intel, Hillsboro, OR January 2013 - July 2013
Principal Validation Architect Engineer - Contract
• Verification Engineer – Analog Mixed-Signal – Hybrid Power Chip
• Validation Engineer – RFID EPC Gen2 (18000-6C)
• Backscatter Circuit Design, Antenna Theory
• Validation Equipment
Insitu, Hood River, OR September 2011 - January 2013
Principal Systems Engineer - Contract
• Validation Engineer – Camera, Video Communications, Ethernet, RS232
• Systems Engineer – Video Systems L-Band, S-Band, Network, Fiber Optics, Bandit video, Avionics/Ground Control Communications, Radio Com, Antenna, Networking
• Circuit Design and Analysis
• Applications, Test, Verification and Validation Engineer for x200
• Temperature and Vibration Test
• Military Thermal, Vibration, EMI/EMC and Environmental specifications and test
Sorella Luna Gallery Owner - Portland, OR July 2009 – Sept 2011
Freescale Semiconductors Inc./Motorola - Austin, TX June 1995 - June 2009
Sr. Electrical Engineer
MIPI Design Lead and Architect - (Nov 2005 - June 2009) MIPI D-PHY Design and Module owner.
M-PHY
Analog/Mixed-Signal TX/RX-modeling simulation and testbench
Clock/Data Recovery Block
4GDigRF
8b/10b Encode/Decode
D-PHY
MIPI DPHY System and Chip Sub-system Architecture Engineer
MIPI DPHY Systems and Module Designer
MIPI System Verification Lead - Functional RTL and Postlayout Simulations
Memories Integration and Memory Functional and BIST Testing
DFT Chain Allocation and Hardblock Assignment
Camera/Display Legacy and MIPI inter-operability at Pad interface
Hardblock Timing Analysis, Postlayout hand-edits
Chip Ball Map, Padring, Pad Pitch/Hardblock Boundary/LEF, Mask Layer strategy,
Power/GND Grid design
Validation Lead - EVB, Brassboard Support, Co-Verification. Test Team Interface.
Test Pin design and map
Architecture Spec, Creation Guide, User Guides and Tutorials
Demonstration and Promotion - Viewfinder validation (MIPI Conference Miami 2007)
Analog Design/Verification Engineer - (February 2001 - Novem...
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